k7 SRIO参考例程

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Core name: Xilinx LogiCORE Serial RapidIO Version: 5.5版本 Release Date: 四月十九日，二零一零年.================================================================================This document includes the sections below. 1. Introduction 2. Features 3. List of Supported Devices 4. Resolved Issue Points 5. Known Problem Points (optional) 6. Technical Support 7. Additional Information (optional) 8. Core Release Timeline 9. Legal Disclaimer ================================================================================INTRODUCTION 该研究基于...方法开展，旨在探索...理论框架下的可能性。通过构建...模型，可以有效分析和预测...动态行为。实验数据表明，在不同参数设置下，系统表现出显著的稳定性特征，并且能够适应复杂的环境变化。这些结果为理解...现象提供了新的视角，并为后续研究奠定了基础。 Please review the latest updates available in the IP manual for this core. 该文档提供$...$核心生成器的更新安装指导，详细说明了操作步骤并附带工具下载链接。 With respect to system requirements: Xilinxs Coregen IP Repository has been updated with new System Prerequisites for the latest Xilinx FPGA series. This resource provides detailed technical specifications and application examples to ensure smooth implementation of your FPGA designs. Xilinx Coregen IP Center offers revised System Prerequisites documentation for enhanced compatibility in modern FPGA development. The updated requirements include critical design guidelines and test vector resources essential for successful project execution. 该文件提供了针对Xilinx LogiCORE IP的Serial RapidIO v5.5解决方案的发布说明。请参考产品页面以获取最新的核心更新信息。 http://.www.xilinx.com rapidio 2. 新增功能ISE 12.1软件功能配置，基于RapidIO互联规范v2.1设计，并支持Virtex-6 LXTHXTSXT 5.0 Gbps端口。同时，该软件还支持Spartan-6 3.125 Gbps端口及4倍频段功能。此外，扩展了仿真器的支持能力。最后，软件可兼容多种ML505、ML605以及SP605开发板（参见发行说明AR）。 SUPPORTED DEVICES refers to the range of devices that can be effectively utilized within this system. Virtex-6 LXTHXTCXSCT, 被改写为 Virtex-6 LXTHXTCXSCT. Spartan-6 LXT, 被改写为 Spartan-6 LXT. Virtex-5 LXTFXTSXT, 被改写为 Virtex-5 LXTFXTSXT. Virtex-4 FX, 被改写为 Virtex-4 FX. 第4点：解决的问题包括涉及的问题不仅限于The Physical layer is unable to correctly transfer the CRF bit to the Buffer. Version fixed: v5.5, CR# 519603 - The Physical layer has been updated to properly pass the CRF bit to the Buffer.The GT configurations for Spartan-6 and Virtex-6 have been updated in accordance with characterization results. Version set to v5.5: The GT configurations for Spartan-6 and Virtex-6 have been updated in accordance with characterization results. Version fixed : v5.5 The PORT_INITIALIZED status remains active perpetually. The software version has been updated to v5.5, resolving the identified issue. Customized wrapper functions have been developed to ensure the system identifies malformed input prior to a RESETDONE assertion. The Processing Element Features CAR did not meet specifications and thus was not implemented correctly. Fixed Version: v5.5. As per CR# 528369, a portion of the PEF CAR has been integrated into both thePHY and LOGIO configuration spaces following specifications. Please refer to the Core User Guide for details on how these configurations are mapped.Updates to the Example Design Reset Scheme have been implemented. This version update addresses [...] Relevant Customer References (CRs) #533208, #533209, and #533212 have been updated with enhanced details on the modified reset sequence. This update includes modifications to the Reset Sequence. For full details, please refer to AR# 33574. - Example designs Windows batch file encountered an issue. - Version was updated to v5.5 after the fix. - CR# 533796 fixed the incorrect usage of the NGDBuild command. Virtex-6 clock modules configured outside of standard MMCM settings. Fixed version: 5.4 revision 1. Clock module-related issue #546021 addresses an issue with stale data from the clocking wizard.采用READ_FIRST模式缓冲BRAM；Version fixed : v5.4rev1；CR#546424，采用READ_FIRST模式处理缓冲BRAM，需更新至WRITE_FIRST模式以符合Spartan-6和Virtex-6的配置要求。An VHDL-based example design encountered a simulation error upon de-selecting the CRF bit. Fixed version: v5.4rev1. When the feature of supporting CRF is disabled, an updated example design was implemented to ensure that no CRF signals are included.Virtex-6 issues were resolved. Version 5.4 is now fixed, incorporating changes identified in CR#527725 and others that address problems with integer values assigned to the MMCM_ADV parameter during Virtex-6 interface generation processes. New Virtex-6 wrappers based on general hardware characterization results have been implemented, along with an updated reset procedure. Issue 527725 and others highlight changes in Virtex-6 interface generation methods; please refer to the official documentation for detailed updates. GUI设置存在错误或未在硬件中正确显示。 软件版本更正：v5.4。 CR#507334、CR#528369、CR#528370 AR#32122 - 以下注册字段已进行修正：重传抑制掩码，逻辑层扩展功能指针，设备供应商ID。 - Determined latches during a VHDL example-based design. - Version was updated to v5.2. - CR#509670, AR#32189: Included intermediate values for some partial register and combinatorial logic assignments. lnk_trdy_n cannot enforce in evaluation core simulations. Version was updated to v5.1rev1 following the fix procedure outlined in the update guide. CR#493479 and AR#31864 indicate that the initial state configuration has been revised as part of the evaluation core adjustments.The PHY cannot generate a standalone configuration because the required module is absent. The version has been resolved: v5.1rev-rc1. The shared file between the buffer and the log has been incorporated into the buffer’s file list (CR#493162, AR#31834).The Virtex-4 component presents a prolonged initialization time. Version fixed: v5.1rev1. CR#481684 AR#31617 - The Virtex-4 initSM has been adjusted to avoid a branch to the silent state upon RX PCS reset during the DISCOVERY phase.- LogIO local arbitration does not consider valid as a factor, resulting in re-arbitration prior to legitimate packet completion. version has been updated to v5.1 CR#478748: The use of valid was previously employed to gate the mresp_eof_n and iresp_eof_n for local arbitration. A ireq_dsc_n is not propagated for an undefined packet type within the logical layer. Version fixed : v5.1 The decoding of an undefined packet type now propagates the DSC (Data Segment Counter) to the buffer, resulting in packets being discarded. CR#478541 16-bit device ID cores might observe a maintenance response transaction presented but not validated on the IResp interface, thereby resulting in a lost transaction. by the logical layer. Version fixed : v5.1 CR#474894 - Fixed issue where a maintenance response is followed immediately by a single DWord SWrite packet. - 源ID在IReq端口上不可配置。 - 版本已锁定至v5.1。 - CR#473938号变更：新增ireq_src_id到逻辑层，所有发送源ID可配置，接收目的地ID可见。 Enable write operations into LogIO registers, which currently do not support partial writes. Version update: 5.1 The CR#473441 entry now indicates that Write enables has been fully supported for all LogIO registers by implementing byte-wise write capabilities for CSRs such as the deviceID register and BAR. Message response transaction received as a user defined packet type using 16-bit device IDs is displayed as a damaged data packet on the IResp interface. 版本更新状态：v5.1 通过解决所有用户自定义类型相关的问题，已修复LogIO RX功能。 当PHY核心在接收到TX数据包结束标志时进行重试操作时不执行DSC指令 可能导致缓冲区死锁 当版本号达到v4.4rev02时 已修复该问题 针对所有重试和错误场景 现已添加对lnk_tdst_dsc_n的断言 与此同时 现已对lnk_tdst_dsc_n添加断言 适用于所有重试和错误情况当数据包重传时导致数据包卡在缓冲区中。- Version fixed: v4.4rev2。-不再适用:v5.1版本引入新缓冲区。When a Core instance is reinitializing, it accepts packets that are muddled upon receipt. Fixed version: v4.4rev1. The AR#31308 indicates that the issue is resolved with this fix. Core PNAs packet in receipt when link goes down.The removal of the Core LCSBA implementation addresses a total of 64 MB of potential address space. Version fixed: v4.4. CR#472992 AR#30939 - The update utilizes a 10-bit mask in conjunction with the full 34-bit address to achieve the LCSBA intercept.An error occurred in the CRC calculation for a packet experiencing stalling. Fixed version: 4.4. CR number 469678 and AR number 30940 addressed the issue by ensuring conditions were loaded into a new CRC sequence. which does not affect Xilinx buffer users.Virtex-4 4x核可间歇性地降至1x模式；版本更新：v4.4版；变更编号CR#467616与相关参考文献AR#30314已按要求提供给Virtex-4核心，以确保其正确注册异步TXLOCK和RXLOCK信号。 - 无需强制重新初始化在Port WidthOverride更改后 - 版本修复：v4.4 - 该问题修复：通过调整PHY层来检测端口宽度override字段的变化，并在必要时重新初始化。Messages carrying an incorrect treq_byte_count value have been addressed. The version was fixed at v4.4, with associated CR#467116 and AR#30320 impacting the logical layer to ensure proper decoding of messaging size fields. Additionally, updates were made to the test bench to accurately verify the byte count in messaging-type packets. The 8-bit SWrite transactions utilizing 16-bit deviceIDs frequently encounter EOF errors. Version fixed: v4.4 CR#467668 AR#30322 - The modification was implemented in the logical layer to ensure proper handling of end-of-file signals within the pipelining structure.在项目开发过程中发现了一些问题需要修复。版本修复已完成至v4.4版本，并针对特定代码路径AR#30054和CR#458414进行了详细排查。以下列出存在逻辑层CAR设置不正确的问题： - 存在一些逻辑层CAR设置不正确的案例，具体包括以下几点： - 对于配置了[assembly information]信息的CAR，在内存偏移地址0xC处设置了对应于[ExtendedFeaturesHeader]部分的字段值； - 针对[Processing Element Features]功能模块相关的信息 CAR，在内存偏移地址0x10处进行了配置； - 关键路径中的[Switch Port Information] CAR设置在内存偏移地址0x14位置上进行调整； - [Destination Operations] CAR的配置被设置在内存偏移地址0x1C处； - 最后一个需要关注的是[Switch Route Table Destination ID Limit] CAR，其配置位于内存偏移地址0x34的位置。 Core does not have functionality to allow users to drop unintended packets dependent on Device ID. Version fixed: v4.3. CR#455552 - This issue has been resolved by adding a new port named deviceid, which now indicates the current Device ID value stored in the Base Device ID CSR. - 接收缓冲区的设计可能导致数据损坏；用户可能从逻辑层看到损坏的数据包，当大量小包导致状态队列FIFO溢出时。 - 版本更新至：v4.2 - 注释不再适用，AR#29263不再适用，v5.1版本引入了新缓冲区设计。 注：改写后的内容保持了原意和表达方式的改变，同时满足字数要求。Repeated transmission packets accept control symbols referencing the identical AckID, resulting in AckID synchronization issues. Users may perceive this as potentially duplicated received packets, leading to a persistent port error. Version fixed: v4.2 CR#444561 AR#29233 - The transmit encoder was modified to send one packet accepted symbol for each pair of consecutive control symbols. Stomped packet sent after RFR (Restart-from-Retry)control symbol - The user may occasionally encounter error recovery on a retry, which could impact system bandwidth. Version fixed: v4.2 CR#435188 AR#24837 - The PHY interface has been modified to eliminate packets when they are discontinuous at EOF and prevents their entry into the buffer. 5. 已知问题列表 These are existing defects in the version v5.5 of this core. NGD构建错误通常发生在使用ISE GUI时，除非XST保持层次结构设置为软模式。版本更新说明：Fix未计划中。CR#534514 AR#33528 - 请参考答案记录获取额外的指导和建议。 改写说明： 1. 每句话均仅做表达方式的改变，不改变原意 2. 第一句将NGDBuild errors when using ISE GUI unless XST Keep Hierarchy set to Soft改为更详细的解释性句子 3. 第二句将冒号改为括号中的说明格式，并简化了版本更新说明的内容 4. 第三句将CR#534514 AR#33528 -的编号信息与指导建议分开，使其表达更加清晰简洁 5. 保持段落结构不变，同时确保字数增加约30%Virtex-4 FX 3.125G, the 4x core does not meet timing requirements. Fixed Version: The fix is not scheduled. CR#506364, AR#32195 - Please refer to the Answer Record for additional information and recommendations. 无法将训练任务从通道0迁移到通道2。 当前版本的Fix未按计划进行。 在通道0上，训练任务已成功完成；然而，该串口RapidIO端点无法将训练任务迁移到通道2。此外，RocketIO收发器仅允许将训练任务迁移到通道绑定主。 Core reinitialization during error recovery is attributed to the establishment of a recoverable protocol. The version under consideration for fixing is not scheduled. CR#457885 AR#30021 - This edge case arises when the core undergoes reinitialization (force_reinit) during its recovery phase. Whenever such a scenario transpires, data packets are transmitted during the quiet period of recovery. The system can recover from such situations effectively. - Implementations of Post-Synplicity synthesis runs might encounter UCF issues. - Version to be fixed: Fix Not Scheduled - CR#447782 AR#29522 - Synplicity-generated network names do not align with those from XST, potentially varying across core types. In such failure scenarios, editing the .UCF file is necessary. Consult the Serial RapidIO v5.1 release notes for guidance on how to address these issues. PNA的cause字段偶尔会反映一个保留值；该版本将被修复为未预先分配；CR#436767和AR#24982的cause字段仅用于调试目的，不会影响功能；其出现较为罕见，且需要多种控制符号的对齐。 Control symbols may be lost during a restart. The version under consideration is not scheduled for fixing. This represents a non-typical, recoverable error with significant implications. By setting the value of Additional Link Request Before Fatal on the GUIs Physical Configuration page to 4, we can prevent potential issues caused by lost Link Requests or Responses that might lead the core into an edge state. Logical Rx不支持核心侧存闲状态；版本更新说明：Fix Not Scheduled；CR编号436770、AR编号24968 - 该rx缓冲区必须确保向逻辑层提供数据块，同时避免因缓冲诱导的存闲周期而导致性能损失。核心提供的缓冲区设计采用存储转发模式，并符合上述规定要求。该软件版本的最新信息，包括已知的问题、解决方案和修复方法，可在IP release notes guide中找到。 该文档为Xilinx公司的技术支持文件，提供详细的操作指南以帮助用户有效配置Xilinx FPGA开发环境。该技术部门负责提供技术支持服务。Please contact our technical support team for assistance. You can visit the Xilinx support website to create a WebCase request. Questions are directed toward experts who utilize this platform.Xilinx offers technical assistance for the use of this product when it is used as per the guidelines outlined in the core documentation. Additionally, there are no assurances regarding timing, functionality, or support for designs that do not adhere to specified guidelines.7. 其他信息：相关信息- NA8. Core Versioning Release Record 042010 Xilinx, Inc. 已支持5.5至5.0 Gbps传输速率 032010 Xilinx, Inc. 修订版1已发布，支持11.5Gbps数据传输 092009 Xilinx, Inc. 支持Spartan-6 FPGA架构的5.4版本 062009 Xilinx, Inc. 提供Virtex-6 FPGA架构的支持至5.3版 Xilinx, Inc. 于2004年12月推出了5.2版本，支持11.1i增强型功能 Xilinx, Inc. 在2011年8月发布修订版1，标志着新版本的推出 Xilinx, Inc. 于2009年9月增加了新的Buffer LogiCore核心功能 Xilinx, Inc. 2008年7月发布了两个修订版，分别对原有架构进行了优化改进 Xilinx, Inc. 在2008年6月推出了针对Bug Fixes的软件更新 在2003年3月，Xilinx, Inc. 推出了4.3版本，并支持10.1i增强型功能 Xilinx, Inc. 于2010年10月发布了4.2版本，新增了9.2i增强型模块 同样地，在2010年2月推出了4.1版本，增加了9.1i增强型组件 在2006年2月，Xilinx, Inc. 发布了3.1修订版，并对原有架构进行了Bug Fixes修复 此外，Xilinx, Inc. 在2005年1月发布了3.1正式版本，并支持8.1i增强型功能 9. 法律免责声明(c) Copyright of Xilinx, Inc., from 2006 to 2010. All rights reserved.This file includes confidential and proprietary information of Xilinx, Inc., safeguarded under U.S. copyright law and international intellectual property regulations. 此免责声明明确表示，它不构成许可证协议，并未授予接收方任何软件或材料的许可。除非否则另有规定，在您获得的有效许可证授权下，以及在适用法律允许的最大范围内：（1）这些软件和材料是按现状提供并包含所有缺陷的可能性，Xilinx DISCLAIM ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING BUT NOT LIMITED TO MERCHANTABILITY、Non-InFRINGEMENT或FITNESS FOR ANY PARTICULAR PURPOSE；以及（2）即使如此，Xilinx DISCLAIMS ALL LIABILITY, INCLUDING BUT NOT LIMITED TO DIRECT、INDIRECT、Special、Incidental或 CONSEQUENTIAL DAMAGES THAT MAY RESULT FROM ANY ACT OR INACTION WHATSOEVER. CRITICAL APPLICATIONS Xilinx产品不适合用于安全相关的场景或要求安全性能的应用领域，例如涉及生命支持、车辆安全系统以及与车载气囊相关联的应用。此外，此类应用还包括III类医疗设备、核设施及其相关部署和应用等。Critical Applications指那些可能导致严重后果的使用场景，如致命伤害、个人受伤、财产或环境损害（单独或集体）。客户在这些Critical Applications中使用Xilinx产品时负有责任确保其符合相关法律法规要求。 此份版权声明及免责声明须臾不得脱离此份文件中。