南亚 NANYA DDR3 规格书和数据表
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本资料包含南亚NANYA DDR3内存的技术规格与性能参数，涵盖各种型号的数据表、电气特性及应用指南。
The 4Gb Double-Data-Rate-3 (DDR3(L)) DRAM is a high-speed CMOS SDRAM with 4,294,967,296 bits. It has an internal configuration as an octal-bank DRAM and is organized either as 64Mbit x 8 I/O x 8 banks or 32Mbit x16 I/O x 8 banks. These synchronous devices achieve double-data-rate transfer rates up to 2133 Mb/sec/pin for general applications.
The chip adheres to all key DDR3(L) DRAM features, and control and address inputs are synchronized with a pair of externally supplied differential clocks. Input signals are latched at the crosspoint where one clock signal (CK rising edge) or its inverse (CK falling edge) is present.
All I/O operations synchronize with either a single-ended DQS or a differential DQS pair in a source-synchronous manner. These devices operate on power supplies of 1.5V ±0.075V or 1.35V (-0.067V/+0.1V) and are available in Ball Grid Array (BGA) packages.
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