ESMT NAND MCP.zip

简介：
The device is a 2,112Mbit memory structured as 64K rows (pages) and columns arranged in a configuration of 2,112x8. Spare memory columns at addresses from column 2,048 to 2,111 are allocated for specific functions. A dedicated data register of size 2,112 bytes is integrated with the memory cell arrays to facilitate data transfer operations between IO buffers and memory during page read and program operations. Page-based read and program operations are executed on a per-page basis, whereas block erasure is performed at the block level. The memory array comprises 2048 individually erasable blocks each containing 128K bytes of storage capacity. This design ensures that bit-level erase operations cannot be directly performed on individual cells within this device.