ModelSim 10.7是一款由 Mentor Graphics 公司开发的强大硬件验证语言仿真工具，主要用于Verilog和VHDL等硬件描述语言的设计与验证。
Mentor, a Siemens business, has released ModelSim 10.7, which offers an integrated debug and simulation environment designed to provide todays FPGA designers with advanced capabilities in a productive work setting.
ModelSim HDL simulator provides FPGA customers with an easy and cost-effective way to accelerate FPGA development, lab setup, and testing. Many FPGA designers often proceed directly to the lab without thoroughly validating their design first. This can result in weeks or even months of inefficient debugging time spent there. Testing in the lab typically offers limited visibility into signals within a design. It may take up to 8 hours just to instrument additional signals or make minor bug fixes during place and route operations.
Simulation, on the other hand, significantly speeds up this debug loop and provides complete signal visibility throughout the entire design process. This allows FPGA designs to reach higher quality standards before entering the lab stage, making any time spent debugging in the lab more productive and focused.
In addition to supporting standard HDLs (Hardware Description Languages), ModelSim enhances both design quality and debug productivity through its award-winning Single Kernel Simulator (SKS) technology. SKS enables seamless mixing of VHDL and Verilog within a single design framework, while also offering platform-independent compilation with the performance benefits of native compiled code.
The graphical user interface is robust, consistent, and intuitive, ensuring all windows are automatically updated based on activity in any other window. For instance, selecting a specific region in the Structure window will simultaneously update related information displayed in the Source, Signals, Process, and Variables windows. Users can edit, recompile, and resimulate without leaving ModelSims environment.
All user interface operations can be scripted for automation purposes or run simulations either interactively or in batch mode according to project requirements. ModelSim is capable of simulating behavioral, RTL (Register Transfer Level), and gate-level code, including VHDL VITAL and Verilog gate libraries, with timing details provided through the Standard Delay Format (SDF).
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