Simetis 10.7

简介：
Mentor, a Siemens business, has introduced ModelSim 10.7, a comprehensive and unified debug and simulation environment that equips today’s FPGA designers with sophisticated capabilities within a highly productive workspace. ModelSim HDL simulator offers FPGA customers a streamlined, cost-effective approach to accelerate FPGA development, facilitate lab startup procedures, and rigorously test their designs. Frequently, FPGA designers dedicate considerable time to preliminary design validation in the laboratory setting, often spanning weeks or even months – a period characterized by inefficient debugging processes. Traditional lab testing provides limited insight into the signals present within the design. A simple place-and-route operation can require as much as eight hours simply to instrument additional signals or address minor bug fixes. In contrast, simulation significantly reduces the debug cycle duration and grants complete visibility into all signals within the design. This enhanced visibility allows for the creation of substantially higher quality FPGA designs before they are deployed for lab debugging, thereby maximizing the productivity and focus of time spent during lab-based troubleshooting. Furthermore, ModelSim expands design quality and debug efficiency by supporting not only standard HDLs but also enabling seamless integration of VHDL and Verilog code within a single design through its award-winning Single Kernel Simulator (SKS) technology. Its unique architecture supports platform-independent compilation while maintaining the exceptional performance typically associated with natively compiled code. The user interface is notably powerful, consistently designed, and intuitively navigable; all windows automatically update in response to activity within any other window—for instance, selecting a specific design region within the Structure window will instantaneously update related windows such as Source, Signals, Process, and Variables. Users can effortlessly edit code, recompile designs, and re-simulate without ever needing to leave the ModelSim environment. All user interface operations are fully scriptable, allowing for batch execution of simulations alongside interactive debugging sessions. ModelSim supports simulation of behavioral, RTL (Register Transfer Level), and gate-level code – including VHDL VITAL and Verilog gate libraries – with timing information derived from the Standard Delay Format (SDF).